Back-end-of-line (BEOL) interconnects, consisting of metal wires and inter-level vias, carry high direct current (DC) in advanced integrated circuit (IC) chip technology. In particular, as IC chip technology advances, the current density required in these metal wires/vias increases with the ever-decreasing dimensions in IC chip technology. Also, self-heating by high current devices raises the temperature of nearby interconnects under circuit operation and makes use of high current carrying BEOL interconnects extremely challenging. For example, a device that uses high current and self-heats (e.g., a resistor, a bipolar transistor, etc.) may heat up an interconnect wire that couples to the device. The high current leads to electro-migration (EM) degradation of the interconnect (via and/or line), causing shorts or opens.
As a result, the current-carrying capability (or the Idc limit specified in the design manuals) is significantly reduced to avoid electro-migration degradation in interconnects. As an example, a direct current limit in a copper interconnect may be reduced by a factor of more than three resulting from a temperature rise of about 15° C. from, for example, 85° C. to 100° C., and by almost a factor of 20 at a 125° C. interconnect temperature. As a result, high direct current at elevated temperatures is almost impossible with conventional interconnect structures.
There are various methods aimed at addressing this reliability issue in metal wires/vias. Known methods, though, result in EM induced voids occurring in any section of the segment, which will cause the wire to eventually open as the void grows in size. Other methods use liners to enclose vias. However, such structures and methods do not provide any means to protect EM damage in metal wires, nor such structures address the EM damage at the via/wire interface.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.